1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having self-aligned contact holes.
2. Description of the Related Art
As the cell pitch is decreased in a semiconductor device, the process margin of forming a contact is also gradually decreased. Thus, the method of forming a self-aligned contact (SAC) has been developed and used. The SAC has some advantages as follows: first, a short will not easily occur, even if a misalignment occurs; second, although the space of a photoresist layer pattern is not made small, it is possible to form a contact hole having a small diameter; third, contact resistance can be decreased due to large contact area despite small contact size.
For this reason, it is expected that the SAC will be a promising method of forming a contact in LSI (Large Scale Integration). FIGS. 1A to 1C are the flow diagrams showing the process steps of a prior art method of forming a contact of a semiconductor device. Referring to FIG. 1A, a device isolation layer is formed on a semiconductor substrate to define an active and an inactive region. A gate electrode layer 4 is formed over the active region of the semiconductor substrate 1 disposing a gate oxide layer therebetween. As well-known in the art, the gate electrode layer 4 includes a gate electrode 4a and a gate mask 4b thereon. The gate mask 4b, for example, is formed of a silicon nitride layer to a thickness of about 1000 .ANG.-2000 .ANG.. A gate spacer 5 is formed on both side walls of the gate electrode layer 4 by etching back a silicon nitride layer to a thickness of about 500 .ANG.-1000 .ANG. by a conventional method.
A thin etch stop layer 6 is formed on the semiconductor substrate 1 to a thickness of about 50 .ANG.-200 .ANG.. The etch stop layer 6, like the gate mask 4B and the gate spacer 5, is formed of a silicon nitride layer.
In FIG. 1B, an interlayer insulating film 8 is formed on the etch stop layer 6. The interlayer insulating film 8 is formed of material which has an etch selectivity with respect to the gate mask 4b, gate spacer 5, and etch stop layer 6. The material is, for example, a BPSG (BoroPhosphoSiligate Gate) or a HDP (High Density Plasma) oxide layer. The interlayer insulating film 8 is formed to a thickness of about 3000 .ANG.-7000 .ANG..
However, the HDP oxide layer has a relatively high stress, so that a silicon pit may be formed subsequent to the ion implanting and annealing process. The filling characteristics of the HDP oxide layer are not as good as those of the BPSG layer. The BPSG layer, which is very porous material, exhibits relatively low stress, compared with the HDP oxide layer. In addition, the filling characteristics of the BPSG layer are good. Therefore, HDP layer is not utilized as an insulating layer in the SAC process and BPSG layer is generally employed instead.
But the BPSG has a very high etch rate, so that a bridge may occur between contacts. The CMP (Chemical Mechanical Polishing) or etch back process is carried out thereon. In the planarization process with a BPSG layer whose etch rate is 5 times higher than that of HDP, the thickness variation of the interlayer insulating layer becomes bad. A photoresist pattern 10 is formed over the planar interlayer insulating film 8 to define contact regions.
Referring to FIG. 1C, the interlayer insulating film 8 is dry etched by utilizing the photoresist pattern 10 as a mask. During this SAC etch process, overetching is generally employed to the insulating layer so as to isolate electrically each contact pad. The interlayer insulating film 8 is etched on condition that it has an etch selectivity with respect to the gate mask 4B, gate spacer 5, and etch stop layer 6. Then the etch stop layer 6 is etched until the semiconductor substrate 1 is exposed.
Especially in the case of BPSG, overetching is generally performed due to its uneven surface topology. Accordingly, a shoulder of the gate is subject to the stress. Contact impurity ions are implanted into the semiconductor substrate 1 so as to decrease contact resistance.
A cleaning process is performed so as to remove a native oxide layer formed on the semiconductor substrate 1. A self-aligned contact 14 is formed, as shown in FIG. 1, by covering the interlayer insulating film 8 including the contact hole 11 with a conductive layer such as a polysilicon, and then etching the resultant structure.
If BPSG layer as the interlayer insulating film 8 is subject to implanting process of impurity ions, its wet etch rate will be more than 10 times higher with respect to the previous step of implanting ions, due to the implanting damage of the interlayer insulating film 8. In the cleaning process , after all, a bridge between contacts is occurred.